MT48LC16M16A2P-75ITD High speed CMOS dynamic random access memory SDR SDRAM Fully synchronous

High speed CMOS dynamic random access memory

Description

• PC100- and PC133-compliant

• Fully synchronous; all signals registered on positive

edge of system clock

• Internal, pipelined operation; column address can

be changed every clock cycle

• Internal banks for hiding row access/precharge

• Programmable burst lengths: 1, 2, 4, 8, or full page

• Auto precharge, includes concurrent auto precharge

and auto refresh modes

• Self refresh mode (not available on AT devices)

• Auto refresh

– 64ms, 8192-cycle refresh (commercial and

industrial)

– 16ms, 8192-cycle refresh (automotive)

• LVTTL-compatible inputs and outputs

• Single 3.3V ±0.3V power supply