Description
The 1Gb DDR2 SDRAM is a high
speed CMOS, dynamic random
access memory containing
Read and write accesses to the DDR2 SDRAM are burst oriented; accesses
start at a selected location and
continue for the burst length of four or eight in a programmed sequence. Accesses begin with the registration
of an Activate command, which is followed by a Read or Write command. The address bits registered
coincident with
the activate command are used to select the ba
nk and row to be accesses
The address bits registered coincident with the Read or Write command
are used to select the start
ing column location for the burst
access and to determine if the Auto
Precharge
command is to be issued.
Prior to normal operation, the DDR2 SDRAM must be initialized. The following sections provide detailed
information covering device initialization, register definition, command descript
ion and device operation.
Feature
JEDEC DDR2 Compliant
– Double-data rate on DQs, DQS,DM bus – 4n Prefetch Architecture
Throughput of valid Commands
– Posted CAS and Additive Latency(AL) Signal Integrity
– Configurable DS for system compatibility – Configurable On-Die Termination
Data Integrity
-Auto Refresh and Self Refresh Modes Power Saving Modes – Power Down Mode
– Partial Array Self Refresh(PASR)
SSTL_18 compliance and Power Supply -VDD/VDDQ=1.70 to 1.90V
-Auto Refresh and Self Refresh Modes Power Saving Modes – Power Down Mode
– Partial Array Self Refresh(PASR)
SSTL_18 compliance and Power Supply -VDD/VDDQ=1.70 to 1.90V
